This configuration is relatively easy to create and conceptualize.
This circuitry must sit idle in sequential processors while other parts are working.
This issue is resolved with an instruction pipeline.
In a pipelined processor, the discrete sections of circuitry are broken apart a little further into pipeline stages.
This separation lets the circuitry for each stage be used constantly.
This is done by starting on the next instruction before the current one is finished.
As many pipeline instructions as possible, stages can be in flight at once.
This doesnt speed up the processing of any individual instruction.
What it does do, however, is dramatically increase the instruction throughput.
For example, suppose an instruction takes five cycles to complete.
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What Does a Pipeline Look Like?
The pipelines in modern CPUs vary in length between manufacturer and CPU architecture.
Some of the longest pipelines in modern consumer CPUs are on the order of 20 stages long.
In the classic RISC pipeline, there are five pipeline stages.
Instruction Fetch is the first stage; it retrieves the instruction to be executed.
Instruction Decode is the second stage; it decodes the retrieved instruction to identify what needs to be done.
Execute is the third stage; its where the computation defined by the instruction is performed.
The final stage is Write Back, where the computation results are written to the destination register.
This is useful but carries some risk.
SettingAto 1 is easy; no issues there.
The problem comes afterward.
Again, youll get the answer 1 when attempting to print A to the screen.
Pipeline stalls or pipeline bubbles can solve this issue.
That is inserting a pause in the pipeline to wait for the dependency on previous instructions to complete.
Unfortunately, this results in a performance penalty, as the CPU sits idle for several cycles.
This avoids the performance impact but is a lot more complex to manage.
Pipeline Flush
Conditional branches cause another similar issue with pipelines.
A branch is an instruction that causes the computer to skip to another code section.
A conditional branch may or may not be taken depending on a condition.
For example, a conditional branch could be taken if the variableAis even or not taken ifAis odd.
you could start processing both options.
Once the correct branch is known, discard the data for the wrong branch.
Or you’re able to attempt to predict which branch will be taken.
The first option significantly impacts performance, as youll just be sitting idle.
Branch prediction is what most modern CPUs do.
With a guess rate above 50%, youre at least doing better than trying both.
Modern algorithms can have success rates of around 95%.
On a successful guess, theres no performance impact.
If you guess wrong, though, the impact can be high.
The instructions for the incorrect branch in flight through the pipeline must be canceled.
This is called a pipeline flush.
Once the pipeline has been flushed, the instructions for the real branch can be started.
Out-of-Order Execution
Out-of-order execution can be the saving grace here.
The conditional branch is then processed as quickly as possible after that.
Additionally, no subsequent dependent instructions are scheduled until the conditional branch is fully processed.
Other unrelated instructions can be used to fill the gaps.
The only issue with this is if there are many conditional branches.
Predicting the taken/not taken outcome of a branching decision can result in no loss of performance about conditional branches.
Choosing incorrectly requires the pipeline to be flushed and then restarted.
