Both SRAM and DRAM are forms of volatile memory.
This means they need a power supply to retain the data they store.
While the method differs, the effect is the same; the data is rendered inaccessible.
The process of escaping the charge is essential for RAM.
Its so important that its the distinguishing feature between SRAM and DRAM.
Static Random Access Memory (SRAM) cells utilize six transistors connected as a pair of cross-coupled inverters.
This structure maintains its charge indefinitely as long as the memory cell has a power supply.
This structure difference also lends itself to the differences in use between SRAM and DRAM.
SRAM is, however, faster than DRAM.
In processor caches, SRAM is used in small quantities, while DRAM provides high-volume system RAM.
DRAM data is read in rows, with a whole row being read at once.
To do so, a rows word line is charged.
This causes the row of memory cells to discharge to their respective bit lines.
The sense amplifiers then latch open and are available to be read.
Data is then read from each specified column into the memory bus to be transferred to the CPU.
While this is very complex, you may have noticed something important.
The reading process discharges the memory cells.
With the cell discharged, rereading them would get all 0s the data would be lost.
Reading DRAM is destructive, but the data stays in your RAM when you read it.
Theres a missing step that explains this discrepancy.
This is done automatically on every read operation and is a refresh operation.
Why Is a Refresh Necessary?
Its easy to understand why its necessary to refresh a memory cell after a destructive read operation.
It is less intuitive why other refreshes are needed.
It just leaks away.
This happens pretty quickly.
The JEDEC standard for current memory standards requires all rows in a DRAM chip to be refreshed every 64ms.
Research has shown that DRAM cells can retain their data for 10 seconds without being refreshed.
Some statistical outliers can even maintain data for up to a minute.
Unfortunately, you also get outliers in the other direction that cant hold their charge even for a second.
A very conservative refresh cycle timer is chosen to avoid data loss or corruption.
Still, modern DRAM is fast enough that refreshing every 64ms doesnt apply an appreciable performance loss.
Occasionally, good cells suddenly become worse at holding their charge, so you cant reliably cherry-pick either.
Research has also found that temperature plays a significant role in the charge decay rate.
Above 85 degrees Celsius charge can decay significantly faster, so the refresh cycle time is halved.
Conversely, cold DRAM can maintain its charge longer.
Conclusion
DRAM cells need regular refreshing to store data long-term for two reasons.
Firstly, the read operation is destructive.
Secondly, the transistors charge decays over time.
The refresh process is generally only necessary every few seconds.
