There are many parts to a computer.

One of the key pieces is system memory or RAM.

This contains all the data the CPU could need for the currently running processes.

memory slots

RAM is the second of four tiers of storage.

The first is CPU cache; the others are long-term storage.

Such as connected HDDs or SSDs, and archival storage, such as disconnected external hard drives.

The CPU can directly access only the CPU cache.

As fast as modern SSDs and RAM can be, theyre just too slow for the CPU.

To manage these data transfers, a gear controller is used.

For storage devices, thats ahard drive controlleror an SSD controller.

For RAM, thats the job of the memory controller.

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Bringing Northbridge Closer to Home

Historically CPUs have had the memory controller located on the Northbridge.

This was half of an external chipset situated on the motherboard.

Its purpose was to provide memory access as well as access to the Southbridge.

The Southbridge was used to connect storage and peripheral devices.

Integrating the Northbridge provided several advantages while also locking in a disadvantage.

This change enabled (then) future generations of RAM to continue to grow in performance.

What Does the Memory Controller Actually Do?

The memory controller requests the data the CPU wants from the RAM.

To prevent data loss, every memory cell row must be periodically refreshed.

Current JEDEC standards specify that all rows are refreshed every 64ms.

To avoid a significant decrease in performance every 64ms, the memory controller doesnt refresh all rows at once.

Instead, it performs rolling opportunistic refreshes on rows that havent been accessed between read or write operations.

Technically, the 64ms period is significantly more conservative than necessary.

Most DRAM cells can actually hold a charge for 10 seconds in standard conditions.

64ms leaves enough buffer to refresh even the worst statistical outliers in charge retention.

The performance impact of being conservative on the refresh rate, however, is minimal.