There are many different layers to addressing DRAM.
Ultimately memory is managed via a row and column address.
There are plenty more layers in between, though.
Memory is accessed over channels.
Each channel is fully independent and can transmit data at the same time.
Note:While the channels are independent, they operate in lockstep and are synchronized.
Its essential to ensure that each populated channel operates at the same speed and has the exact timings.
Ideally, all connected DIMMs should be identical and from one kit.
Non-identical RAM can cause stability issues.
If DIMMs of different speeds are connected, the fastest will be limited to the slowest speed.
On a DIMM, you have one or more ranks of DRAM chips.
This works because data is spread across all the DRAM chips in a rank.
8 DRAM chips are needed to provide 64 bits of data to the data pins.
Each chip has several banks.
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Banking on DRAM
In a single DRAM chip, there are multiple banks.
The DDR4 spec allocates 4 bits to address banks, allowing for 16 banks per DRAM chip.
Each bank is generally independent and can be in any phase of the access/refresh cycle.
All banks have only one set of data pins.
This configuration limits the DRAM chip to having only one bank transmitting or receiving data per clock cycle.
Another key thing to know about banks is that they are entirely synchronized across a rank of DRAM chips.
This synchronization is so complete that banks can be considered spanning all the DRAM chips in the rank.
All DRAM chips in the rank will open row three, column four, in the second bank.
Each will return 8 bits of data.
Additionally, bank one can close its open row to prepare it to open a new one.
Bank 7 can complete a read operation at the same time.
However, it cant send the data simultaneously as all banks share the same set of data pins.
Bank 7 must wait for the data pins to be free to transmit its data.
